Select device for memory cell applications

ABSTRACT

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No.15/215,659 filed Jul. 21, 2016, which is a Divisional of U.S.application Ser. No. 14/515,998 filed Oct. 16, 2014, now U.S. Pat. No.9,425,390, the specifications of which are incorporated herein byreference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory devicesand methods, and more particularly, to select devices for memory cellapplications.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory, including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), resistive memory, and flashmemory, among others. Types of resistive memory include programmableconductor memory, and resistive random access memory (RRAM), amongothers.

Memory devices are utilized as non-volatile memory for a wide range ofelectronic applications in need of high memory densities, highreliability, and data retention without power. Non-volatile memory maybe used in, for example, personal computers, portable memory sticks,solid state drives (SSDs), digital cameras, cellular telephones,portable music players such as MP3 players, movie players, and otherelectronic devices.

RRAM devices include resistive memory cells that store data based on theresistance level of a storage element. The cells can be programmed to adesired state, e.g., corresponding to a particular resistance level,such as by applying sources of energy, such as positive or negativevoltages to the cells for a particular duration. Some RRAM cells can beprogrammed to multiple states such that they can represent, e.g., store,two or more bits of data.

The programmed state of a resistive memory cell may be determined, e.g.,read, for example, by sensing current through the selected resistivememory cell responsive to an applied interrogation voltage. The sensedcurrent, which varies based on the resistance level of the memory cell,can indicate the programmed state of the resistive memory cell.

In various instances, arrays of resistive memory cells can be prone toread disturbance problems. For instance, as part of a read operation,current can flow from a selected access line, e.g., word line, through aselected memory cell, to a data/sense line, e.g., bit line. However, invarious array architectures such as cross-point architectures, currentalso flows into unselected word lines that cross over the selected bitline. Conduction of current into unselected word lines can reduce theability to distinguish between data states, e.g., by decreasing outputimpedance, among other drawbacks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a portion of an array of resistive memorycells in accordance with one or more embodiments of the presentdisclosure.

FIG. 2A illustrates a cross-sectional view of a select device inaccordance with one or more embodiments of the present disclosure.

FIG. 2B illustrates a top view of the select device illustrated in FIG.2A in accordance with one or more embodiments of the present disclosure.

FIG. 3A-1 illustrates a cross-sectional view of a select device inaccordance with one or more embodiments of the present disclosure.

FIG. 3B-1 illustrates a top view of the select device illustrated inFIG. 3A-1 in accordance with one or more embodiments of the presentdisclosure.

FIG. 3A-2 illustrates a cross-sectional view of a select device inaccordance with one or more embodiments of the present disclosure.

FIG. 3B-2 illustrates a top view of the select device illustrated inFIG. 3A-2 in accordance with one or more embodiments of the presentdisclosure

FIG. 4A illustrates a cross-sectional view of a select device inaccordance with one or more embodiments of the present disclosure.

FIG. 4B illustrates a top view of the select device illustrated in FIG.4A in accordance with one or more embodiments of the present disclosure.

FIG. 5 is a graph illustrating voltage and current relationships of aselect device in accordance with one or more embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The present disclosure includes select devices and methods of usingselect device for memory cell applications. An example select deviceincludes a first electrode having a particular geometry, a semiconductormaterial formed on the first electrode and a second electrode having theparticular geometry with formed on the semiconductor material, whereinthe select device is configured to snap between resistive states inresponse to signals that are applied to the select device.

Embodiments according to the present disclosure can include a selectdevice that snaps between a first resistive state and a second resistivestate in response to signals above a threshold voltage being applied toand then removed from the select device. As an example, embodiments ofthe present disclosure can support current densities greater than 1MA/cm² when the select device is in the first resistive state inresponse to the signal applied to the select device being greater thanthe threshold voltage. Embodiments of the present disclosure can includebenefits such as providing a bi-directional select device useful formemory applications such as resistive memory applications, for instance.As an example, one or more select devices in accordance with the presentdisclosure can be formed at temperatures sufficiently low to supportback end of line processing (BEOL) when forming memory arrays such asRRAM arrays. Various embodiments provide select devices having a high oncurrent versus off current ratio (Ion/Ioff) in association with apartial select read method, such as a half select read method or thirdselect read method. That is, Ion/Ioff at an on voltage (Von) associatedwith the memory array is much greater than Ion/Ioff at a correspondinghalf select voltage (Von/2) or third select voltage (Von/3). As anexample, Ion/Ioff at Von can be at least 1×10⁴ times greater than theIon/Ioff at Von/2, in some embodiments. Various embodiments includeleakage currents of a select device that scale with the area of a selectdevice.

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure. As used herein, the designators “M” and “N”,particularly with respect to reference numerals in the drawings,indicates that a number of the particular feature so designated can beincluded. As used herein, “a number of” a particular thing can refer toone or more of such things (e.g., a number of memory devices can referto one or more memory devices).

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, 208 may referenceelement “08” in FIG. 2A, and a similar element may be referenced as 308in FIG. 3A. As will be appreciated, elements shown in the variousembodiments herein can be added, exchanged, and/or eliminated so as toprovide a number of additional embodiments of the present disclosure.

FIG. 1 is a block diagram of a portion of an array 100 of memory cellsin accordance with one or more embodiments of the present disclosure.The array 100 is a two terminal cross-point array having memory cellslocated at the intersections of a number of access lines 102-0, 102-1, .. . , 102-N, which may be referred to herein as word lines, and a numberof data/sense lines 104-0, 104-1, . . . , 104-M, which may be referredto herein as bit lines. As illustrated, the word lines 102-0, 102-1, . .. , 102-N are parallel to each other and are orthogonal to the bit lines104-0, 104-1, . . . , 104-M, which are substantially parallel to eachother; however, embodiments are not so limited.

Each memory cell may include a storage element 106, e.g. a resistivememory element, coupled in series with a select device 108, e.g., anaccess device, in accordance with one or more embodiments describedherein. The storage element 106 can include a programmable portion thatmay have a variable resistance, for example. The storage element 106 caninclude, for example, one or more resistance variable materials such asa transition metal oxide material or a perovskite including two or moremetals, e.g., transition metals, alkaline earth metals, and/or rareearth metals. Other examples of resistance variable materials associatedwith the storage element 106 of a memory cell can include chalcogenides,binary metal oxides, colossal magnetoresistive materials, and/or variouspolymer-based resistive variable materials, among others. As such, thememory cells can be RRAM cells, PCRAM cells, and/or conductive bridgingmemory cells, among various other types of resistive memory cells.

In one or more embodiments, the select devices 108 corresponding to eachmemory cell include a first electrode, a semiconductor material, and asecond electrode. The first electrode, the semiconductor material, andthe second electrode of the select devices can be configured so thatthey snap between a first resistive state and a second resistive statewhen a signal is applied to select device 108. For example, selectdevice 108 can snap from a first resistive state to a second resistivestate when a signal that is greater than a threshold voltage is appliedto select device 108. Therefore, when a signal that is greater than thethreshold voltage is applied to select device 108, the select devicesnaps to the second resistive state and a current associated withprogramming and/or reading a memory cell can pass through the selectdevice to storage element 106. Once the signal is removed from theselect device 108, the select device 108 snaps back to the firstresistive state. In a number of embodiments, the select device 108 canrepeatedly snap between resistive states when a signal is applied to theselect device and removed from the select device 108.

In a number of embodiments, select device 108 can be configured so thata first resistive state of the select device does not allow currentassociated with programming and/or reading a memory cell to pass throughthe select device 108 to the storage element 106 of a memory cell. Also,select device 108 can be configured so that a second resistive state ofthe select device allows current associated with programming and/orreading a memory cell to pass through the select device 108 to thestorage element 106 of a memory cell. In a number of embodiments, selectdevice 108 can be configured so that a storage element 106 of a memorycell can see a current density of greater than 1 MA/cm² when the selectdevice 108 is in a resistive state associated with a signal greater thana threshold voltage.

In a number of embodiments, the select device 108 can be configured tosnap between resistive states when a signal is applied to the selectdevice 108 based on the size of the select device 108 and the materialscomprising the select device 108. For example, the threshold voltagewhere the snap between resistive states occurs can be configured basedon the size of the select device 108 and the materials comprising theselect device 108. In a number of embodiments, select device 108 caninclude a first electrode and a second electrode configured in acircular geometry having a diameter of less than approximately 30nanometers. The select devices 108 can include a semiconductor materialbetween two electrodes and the semiconductor material and the twoelectrodes can be doped with an optical adsorber, such as carbon, forexample. Also, an insulating material can be formed on the sidewalls ofthe two electrodes and the semiconductor material. The insulatingmaterial can control the heat loss in the semiconductor material so thatthe select device can have desired resistive properties. For example,doping the electrodes and/or semiconductor material with carbon and/orproviding an insulating material on the sidewalls of the electrodes andsemiconductor material can provide the select device 108 with thermalproperties to reach a temperature where the select device snaps betweenresistive states when a voltage, such as a programming and/or readsignal, is applied to the select device. For example, various thermal,electrical, and structural properties of the select device 108 can beconfigured so that storage element 106 and select device 108 can beoperated together with control circuitry. In a number of embodiments,select device 108 can be configured to operate between approximately 0.1V to 10V and snap between resistive states with a current that is lessthan approximately 1 μA. For example, select device 108 reaches atemperature of greater than 600° C. when a signal of 0.5V to 5V, with acorresponding current of approximately 1 nA to 100 nA, is applied to theselect device 108. In a number of embodiments, the leakage current ofthe select device 108 when applying a half select voltage or a thirdselect voltage, for example, can be less than approximately 1 μA. Forexample, when a half select voltage is applied to select device 108, theleakage current of the select device can be less than approximately 10nA.

As an example, the array 100 can be operated in accordance with a halfselect method, e.g., a half select biasing scheme. A half select methodcan include applying a half select voltage (V/2) to a selected bit line,e.g., a bit line coupled to a selected memory cell, and a negative halfselect voltage (−V/2) to a selected word line, e.g., a word line coupledto the selected memory cell, while biasing unselected word lines at areference potential, e.g., a ground potential. In the exampleillustrated in FIG. 1, memory cell 105 is a selected memory cell. Thatis, selected memory cell 105 is coupled to a selected bit line 104-1biased at V/2 and a selected word line 102-1 biased at −V/2. As such,the full select voltage (V) is applied across the selected memory cell105. The unselected memory cells coupled to the selected bit line 104-1and selected word line 102-1, e.g., unselected memory cells 107-0 and107-1, experience a half select voltage of +/−V/2 and can be referred toas “half selected” cells. The unselected memory cells coupled tounselected bit lines and/or word lines are unbiased, e.g., theyexperience a ground potential of 0V, in this example. The select voltage(V) can be a write voltage or a read voltage, for instance.

It can be beneficial for select devices to provide a half select ratio(HSR) that is as large as possible. The HSR can refer to the ratio ofthe current flowing through a selected memory cell, e.g., 105, to thecurrent flowing through a half selected memory cell, e.g., 107-0 and107-1. As described further below, select devices in accordance with oneor more embodiments can provide a half select ratio of 10⁴:1 to 10⁵:1 orlarger, for example. The larger the HSR, the lower the power dissipationcaused by current flow in half-selected memory cells, e.g., 107-0 and107-1, and the greater the signal to noise ratio (S/N) during readand/or write operations, which can reduce the likelihood of read and/orwrite disturb to half selected memory cells. The half select method isprovided as one example and embodiments are not limited to a particularprogramming and/or read method.

Embodiments of the present disclosure are not limited to a half selectmethod associated with programming or reading a memory cell. Forinstance, the array 100 can be operated in accordance with other biasingschemes, such as a one third select method. As an example, a one thirdselect method can include applying a full select voltage (V) to aselected bit line and a ground potential to a selected word line, whilebiasing unselected bit lines at V/3 and unselected word lines at (2V)/3,such that the voltage between unselected word lines and bit lines isabout +/−V/3.

In various embodiments, the select devices 108 corresponding to memorycells of array 100 can be “bipolar” in that they permit bi-directionalcurrent flow, e.g., in both forward and reverse directions, undersufficiently high voltage bias conditions, but block current flow underlower voltage conditions.

FIG. 2A illustrates a cross-sectional view of a select device 208 inaccordance with one or more embodiments of the present disclosure. InFIG. 2A, select device 208 includes electrodes 210 and a semiconductormaterial 212. In a number of embodiments, electrodes 210 can includematerial such as titanium silicon nitride (TiSiN), tantalum nitride(TaN), and/or carbon, for example. In a number of embodiments,electrodes 210 can include a metal doped with carbon. Also, electrodes210 can include number of portions, such as a laminate formed ofportions of a metal, portions of a resistor, and/or portions of asemiconductor. The electrodes 210 can include portions of asemiconductor that can include silicon (Si), silicon germanium (SiGe),germanium (Ge), silicon carbon (SiC), aluminum nitride (AlN), carbon,and/or diamond like carbon (DLC), among other semiconductors. Theportions of semiconductors included in the electrodes 210 can be dopedwith a metal. The semiconductors can be doped with approximately 1E14³atoms of the dopant metal, for example. A semiconductor portion includedin the electrodes 210 can be approximately 5 nm-50 nm thick.

In a number of embodiments, the electrodes can include a number ofportions of material that interface with the semiconductor material 212.The number of materials can include combination of materials thatinterface and can act as a thermal boundary resistance, which can limitheat dissipation through the electrodes 210 to the semiconductormaterial 212. The portions of materials can be formed of a number ofportions of materials interfacing together that include tungsten/carbon(W/C), tungsten silicon/carbon (WSi_(x)/C), tungsten nitride/carbon(WN/C), titanium/carbon (Ti/C), tungsten/silicon carbide (W/SiC),tungsten/doped polycrystalline semiconductor, tungsten silicon/dopedpolycrystalline semiconductor, and/or tungsten nitride/dopepolycrystalline semiconductor, among other material combinations. Forexample, the polycrystalline semiconductors can be silicon (Si), silicongermanium (SiGe), germanium (Ge), silicon carbide (SiC), and/or aluminumnitride (AlN) doped with arsenic (As), boron (B), phosphorus (P),titanium (Ti), aluminum (Al), antimony (Sb), tin (Sn), indium (In),and/or bismuth (Bi), among other materials. Also, a portion of carbon(C) or tungsten silicon (WSi_(x)) can be formed between the electrodes210 and the semiconductor material 212. The portion of carbon (C) ortungsten silicon (WSi_(x)) can be approximately 1 nm-30 nm thick and canhelp prevent metal electro-migration between the electrodes 210 and thesemiconductor material 212.

In a number of embodiments, semiconductor material 212 can includeamorphous silicon. Also, the amorphous silicon can be doped with carbonto increase the thermal capacitance of the semiconductor material 212.The semiconductor material 212 can be configured so that the resistivestate changes in response to the semiconductor material 212 heating to atemperature of greater than 600° C. when a signal that is between 0.5Vand 5V is applied to the select device 208.

FIG. 2B illustrates a top view of the select device 208 illustrated inFIG. 2A in accordance with one or more embodiments of the presentdisclosure. As illustrated in FIG. 2B, select device 208 can have acircular geometry. The electrodes 210 of select device can have adiameter of approximately 100 nanometers or less. The semiconductormaterial 212, not shown in FIG. 2B, can have the same circular geometryas the electrodes. In a number of embodiments, the select device 208 andthe electrodes 210 can have an aspect ratio that is greater than 10. Theselect device and the electrodes 210 having such aspect ratios canincrease the thermal resistance of the select device and reduce thermalsink effects in the select device. In a number of embodiments, thesemiconductor material 212 can have a different geometry and/or sizethan electrodes 210. For example, the semiconductor material 212 couldhave a diameter that is less than the diameter of the electrodes 210. Ina number of embodiments, the electrodes 210 and/or semiconductormaterial 212 can have a quasi-square geometry, among other geometries.In a number of embodiments, a vacuum can be formed between adjacentselect devices. A vacuum between adjacent select devices can providethermal insulation, which can to reduce the thermal effects on aparticular select device when heating and/or cooling adjacent selectdevices.

FIG. 3A-1 illustrates a cross-sectional view of a select device 308 inaccordance with one or more embodiments of the present disclosure. InFIG. 3A-1, select device 308 includes heaters 314, electrodes 310 and asemiconductor material 312. In a number of embodiments heaters 314 canbe in contact with the electrodes 310. The heaters 314 can be formed ofmetals and/or carbon, among other materials that can increase thethermal capacitance of the select device 308. In a number ofembodiments, electrodes 310 can include materials such as titaniumsilicon nitride (TiSiN), tantalum nitride (TaN), and/or carbon, forexample. In a number of embodiments, electrodes 310 can include a metaldoped with carbon. Also, electrodes 310 can include a laminate formed ofportions of a metal and portions of a resistor. In a number ofembodiments, semiconductor material 312 can include amorphous silicon.Also, the amorphous silicon can be doped with carbon to increase thethermal capacitance of the semiconductor material 312.

FIG. 3B-1 illustrates a top view of the select device 308 illustrated inFIG. 3A-1 in accordance with one or more embodiments of the presentdisclosure. As illustrated in FIG. 3B-1, select device 308 can have acircular geometry. The heaters 314 and electrodes 310, not shown in FIG.3B-1, of select device 308 can have a diameter of approximately 30nanometers or less. The semiconductor material 312, not shown in FIG.3B-1, can have the same circular geometry as the electrodes. In a numberof embodiments, the semiconductor material 312 can have a differentgeometry and/or size than electrodes 310 and/or heaters 314. Forexample, the semiconductor material 312 could have a diameter that isless than the diameter of the electrodes 310 and/or heaters 314. In anumber of embodiments, the electrodes 310, heaters 314, and/orsemiconductor material 312 can have a quasi-square geometry, among othergeometries.

FIG. 3A-2 illustrates a cross-sectional view of a select device 308 inaccordance with one or more embodiments of the present disclosure. InFIG. 3A-2, select device 308 includes electrodes 310, heaters 314, and asemiconductor material 312. In a number of embodiments, electrodes 310can be in contact with the heaters 314. In a number of embodiments,electrodes 310 can include materials such as titanium silicon nitride(TiSiN), tantalum nitride (TaN), and/or carbon, for example. In a numberof embodiments, electrodes 310 can include a metal doped with carbon.Also, electrodes 310 can include a laminate formed of portions of ametal and portions of a resistor. The heaters 314 can be formed ofmetals and/or carbon, among other materials that can increase thethermal capacitance of the select device 308. In a number ofembodiments, semiconductor material 312 can include amorphous silicon.Also, the amorphous silicon can be doped with carbon to increase thethermal capacitance of the semiconductor material 312.

FIG. 3B-2 illustrates a top view of the select device 308 illustrated inFIG. 3A-2 in accordance with one or more embodiments of the presentdisclosure. As illustrated in FIG. 3B-2, select device 308 can have acircular geometry. The electrodes 310 and the heaters 314, not shown inFIG. 3B-2, of select device 308 can have a diameter of approximately 30nanometers or less. The semiconductor material 312, not shown in FIG.3B-2, can have the same circular geometry as the electrodes. In a numberof embodiments, the semiconductor material 312 can have a differentgeometry and/or size than electrodes 310 and/or heaters 314. Forexample, the semiconductor material 312 could have a diameter that isless than the diameter of the electrodes 310 and/or heaters 314. In anumber of embodiments, the electrodes 310, heaters 314 and/orsemiconductor material 312 can have a quasi-square geometry, among othergeometries.

FIG. 4A illustrates a cross-sectional view of a select device 408 inaccordance with one or more embodiments of the present disclosure. InFIG. 4A, select device 408 includes electrodes 410, a semiconductormaterial 412, and an insulating material 416. In a number ofembodiments, electrodes 410 can include material such as titaniumsilicon nitride (TiSiN), tantalum nitride (TaN), and/or carbon, forexample. In a number of embodiments, electrodes 410 can include a metaldoped with carbon. Also, electrodes 410 can include a laminate formed ofportions of a metal and portions of a resistor.

In a number of embodiments, semiconductor material 412 can includeamorphous silicon. Also, the amorphous silicon can be doped with carbonto increase the thermal capacitance of the semiconductor material 412.The insulating material 416 can be formed on the sidewalls of theelectrodes 410 and the semiconductor material 412. The insulatingmaterial 416 can include silicon dioxide (SiO₂), silicon nitride (SiN),boron nitride (BN), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂),hafnium oxide (HfO₂) doped with less than 50% yttrium oxide (Y₂O₃),zirconium oxide (ZrO₂), zirconium oxide (ZrO₂) doped with between 4% and8% yttrium oxide (Y₂O₃), yttrium oxide (Y₂O₃), titanium oxide (TiO₂),yttria-stabilized zirconia (YSZ), and/or pyrochlore oxides, for example,among other insulating materials. The insulating material 416 canprovide thermal insulation to allow the semiconductor material to heatto a temperature where a resistive state of the semiconductor materialsnaps to a different resistive state. In a number of embodiments,insulating material can be formed so that there is a vacuum between theinsulating material and the sidewalls of the semiconductor material andthe electrode material. The vacuum between the insulating material andthe sidewalls of the semiconductor material and the electrode materialcan provide thermal insulation to facilitate the heating and/or coolingof the semiconductor material.

FIG. 4B illustrates a top view of the select device 408 illustrated inFIG. 4A in accordance with one or more embodiments of the presentdisclosure. As illustrated in FIG. 4B, select device 408 can have acircular geometry. The insulating material 416 and electrodes 410 ofselect device 408 can have a combined diameter of approximately 30nanometers or less. The semiconductor material 412, not shown in FIG.4B, can have the same circular geometry as the electrodes. In a numberof embodiments, the semiconductor material 412 can have a differentgeometry and/or size than insulating material 416 and electrodes 410.For example, the semiconductor material 412 could have a diameter thatis less than the diameter of the insulating material 416 and electrodes410. In a number of embodiments, the electrodes 410, insulating material416, and/or semiconductor material 412 can have a quasi-square geometry,among other geometries.

FIG. 5 is a graph illustrating voltage and current densityrelationships, e.g., a JV graph, of a select device in accordance withone or more embodiments of the present disclosure. In FIG. 5, JV graph520 includes line 522 that illustrates the relationship of the currentdensity on a select device, such as select devices 108, 208, 308, 408described in association with FIGS. 1-4, when a signal, such aprogramming signal and/or a read signal, is applied to the selectdevice.

In one or more embodiments, when a signal, e.g., a first signal, havinga voltage that ramps from approximately 0 V to approximately 3.2 V, thecurrent density on the select device starts to increase significantlyonce the signal reaches a threshold voltage, which is approximately 3.2V on graph 520. For example, the current density on the select deviceranges from approximately 1E1 A/cm² to 1E5 A/cm², when the signal isramped from approximately 0 V to 3.5 V, while the current density on theselect device ranges from approximately 1E5 A/cm² to 2E7 A/cm², when thesignal is ramped from approximately 3.2 V to 3.5 V. The currentcorresponding to the voltage ranging from 0V to 3.2 V can range fromapproximately 1E-10V to approximately 1E-4 V. The increase of thecurrent density on the select device is caused by a drop in resistanceof the select device due to the signal heating the select device havingthe materials and geometry described herein. The select devicesdescribed herein can withstand repeated heating to temperatures greaterthan 600° C. without breaking down. For example, applying a signal thatis ramped from 0 V to 3.5 V causes the select device heat up. When theselect device reaches a threshold temperature (T_(T)) due to the voltageof the signal applied to the select device increasing, the select devicesnaps between resistive states and the resistance of select devicedecreases by a number of orders of magnitude. FIG. 5 illustrates aselect device that is configured to reach a threshold temperature, wherethe select device snaps between resistive states, which is greater than600° C. when a signal that is greater than or equal to approximately 3.2V is applied to the select device. Once the select device snaps betweenresistive states and the resistance of the select device decreases, thesignal is passed from the select device to a storage element of a memorycell with a magnitude of current that is sufficient to program and/orread the memory cells.

In FIG. 5, graph 520 includes line 524 that illustrates the relationshipof the current density on a select device, such as select devices 108,208, 308, 408 described in association with FIGS. 1-4, when a signal,such a programming signal and/or a read signal, is removed from theselect device.

In one or more embodiments, line 524 on graph 520 illustrates as asignal, e.g., a first signal, having a voltage of approximately 3.5V isremoved from the select device causing the voltage on the select deviceto decrease. As the voltage on the select device decreases, thetemperature of select device decreases, which causes the resistance ofthe select device to increase and also the current density on the selectdevice to decrease. In FIG. 5, as the signal is removed from selectdevice, the current density on the select device decreases fromapproximately 2E7 A/cm² to 1E4 A/cm², as the voltage of the signaldecreases from approximately 3.5V to 2V. While the current density onthe select device decreases from approximately 1E4 A/cm² to 1E1 A/cm²,as the voltage of the signal decreases from approximately 2V to 0V. Thedecrease in current density on the select device that starts when thevoltage on the select device is approximately 2V can correspond with thetemperature of the select device cooling to below a thresholdtemperature, where the select device snaps between resistance states.For example, the resistance of the select device can snap from a secondresistance state to a first resistance state, where the first resistancestate is a number of orders of magnitude higher than the secondresistance state, when the select device cools to below the thresholdtemperature. In a number of embodiments, the select device can snapbetween resistive states less than 15 ns after a signal is removed fromthe select device. Once the select device snaps between resistive statesand the resistance of the select device increases, the select device isin a resistive state where signals, e.g., a second signal, applied tothe select device that are less than a threshold voltage do not passfrom the select device to a storage element of a memory cell with amagnitude of current that is sufficient to program and/or read thememory cells.

The present disclosure includes select devices and methods of usingselect device for memory cell applications. An example select deviceincludes a first electrode having a particular geometry, a semiconductormaterial formed on the first electrode and a second electrode having theparticular geometry with formed on the semiconductor material, whereinthe select device is configured to snap between resistive states inresponse to signals that are applied to the select device.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of various embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the various embodiments ofthe present disclosure includes other applications in which the abovestructures and methods are used. Therefore, the scope of variousembodiments of the present disclosure should be determined withreference to the appended claims, along with the full range ofEquivalents to which such claims are entitled.

In the foregoing Detailed Description, various features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

What is claimed is:
 1. A method of forming a memory cell, the methodcomprising: forming a select device, wherein the select device includes:a first electrode having a particular geometry; a first heater formed onthe first electrode; a semiconductor material formed on the firstheater; a second heater formed on the semiconductor material; and asecond electrode having the particular geometry formed on the secondheater; and forming a storage element in series with the select device.2. The method of claim 1, wherein forming the select device is a backend of line (BEOL) process.
 3. The method of claim 1, wherein a width ofthe particular geometry is based on an operating voltage associated withthe memory cell.
 4. The method of claim 1, wherein a composition of thesemiconductor material is based on an operating voltage associated withthe memory cell.
 5. The method of claim 1, wherein the method includesforming the select device at a temperature of not greater thanapproximately 450° C.
 6. The method of claim 1, wherein forming theselect device includes the first electrode having a circular geometry.7. The method of claim 1, wherein forming the select device includes thefirst electrode having a quasi-square geometry.
 8. A method of forming amemory cell, the method comprising: forming a select device, whereinforming the select device includes: forming a first heater; forming afirst electrode on the first heater; forming a semiconductor material onthe first electrode; forming a second electrode on the semiconductormaterial; and forming a second heater on the second electrode; andforming a storage element in series with the select device.
 9. Themethod of claim 8, wherein the method includes forming a vacuum betweenthe select device and an adjacent select device of an array.
 10. Themethod of claim 8, wherein the method includes doping the first andsecond electrodes with an optical absorber.
 11. The method of claim 8,wherein forming the first electrode includes forming a first laminateportion that includes a metal, a resistive material, or anothersemiconductor material.
 12. The method of claim 8, wherein forming thefirst heater includes forming a metal.
 13. A method of forming a memorycell, the method comprising: forming a select device of the memory cell,wherein the select device includes: a first electrode and a secondelectrode; a first heater and a second heater, wherein the first heateris coupled to the first electrode and the second heater is coupled tothe second electrode; and a semiconductor material between the first andsecond electrodes, wherein the first heater and first electrode areadjacent to a first surface of the semiconductor material and the secondheater and second electrode are adjacent to a second surface of thesemiconductor material; and wherein the select device is configured to:snap from a first resistive state to a second resistive state inresponse to providing a first signal provided thereto, wherein the firstsignal is greater than a threshold voltage; and remain in the firstresistive state in response to a second signal provided thereto, whereinthe second signal is less than the threshold voltage; and forming astorage element in series with the select device.
 14. The method ofclaim 13, wherein the method includes forming the select device suchthat: a first current density is provided to the storage element inresponse to the select device snapping from the first resistive state tothe second resistive state; and a second current density is provided tothe storage element in response to the select device remaining in thefirst resistive state.
 15. The method of claim 14, wherein the firstcurrent density is greater than 1 MA/cm² and the second current densityis less than or equal to 1 MA/cm².
 16. The method of claim 15, whereinthe method includes forming the select device such that the selectdevice snaps from the second resistive state to the first resistivestate in response to removing the first signal.
 17. The method of claim13, wherein the method includes forming the select device such that theselect device reaches a temperature greater than 600° C. in response toproviding the first signal to the select device.
 18. The method of claim13, wherein the method includes forming the select device such that: theselect device snaps from the first resistive state to the secondresistive state in response to reaching a threshold temperature greaterthan 600° C.; and the select device repeatedly reaches the thresholdtemperature.
 19. The method of claim 13, wherein forming the selectdevice includes the first heater formed of a metal.
 20. The method ofclaim 13, wherein the threshold voltage is approximately 2.5 V.